1. Field of the Invention
The present invention relates generally to non-volatile semiconductor memories, and more particularly to an electrically erasable and programmable read-only memory (EEPROM) device including an array of memory cells each having a metal-oxide semiconductor (MOS) transistor structure with a charge storage layer and a control gate.
2. Description of the Related Art
Recently, non-volatile semiconductor memory devices have been developed which has an array of memory cells each of which consists of one metal oxide semiconductor (MOS) transistor in order to improve the memory integration density. Each memory cell is a MOS transistor with a twin-gate structure having a floating gate electrode serving as a charge accumulating layer and a control gate electrode that is to be connected to a program line associated therewith. A preselected number of memory cell transistors are connected in series with one another, and are grouped together in a memory cell group. This cell group is connected to a corresponding data transfer line associated therewith. Such cell group is generally called "NAND cell unit." A plurality of NAND cell units are arranged on a chip substrate to obtain a memory cell matrix configuration. With such a non-volatile memory device, the number of transistors required to form the memory cell matrix can be minimized, thereby to achieve the maximum memory integration on the chip substrate of the limited surface area. Due to the technical advantage, the non-volatile semiconductor memory devices of this type keep receiving industrially hot attention.
A NAND cell type EEPROM is one of the most typical non-volatile semiconductor memory devices of the above type. In the memory, each of a plurality of NAND cell units is provided with an insulated gate MOS transistor serving as a select transistor. By causing the select transistor to turn on, the NAND cell unit may be selectively coupled to a corresponding data transfer line associated therewith, which is called the "bit line." To write (program) data into a target memory cell transistor which is selected from among those in the NAND cell unit, proper control voltages are applied to the memory cell transistors of the subject NAND cell unit, causing charge particles (electrons) to tunnel toward the floating gate only in the target cell transistor so that the threshold value of that selected cell transistor is varied. A logic "1" or "0," which is supplied by the bit line associated with the subject NAND cell unit, is selectively programmed in the target memory cell.
An erase operation is performed by applying different kinds of control voltages to the NAND cell unit such that the charge storage state at the floating gate electrode or electrodes becomes opposite to that in the write operation, thereby discharging by tunneling the charge particles from the floating gate electrode to the substrate. Employing this control voltage applying scheme can ensure an electrical erase function selectively or globally among the memory cells in the EEPROM.
Recently, there is a strong demand for a further improvement in the memory integration density even in NAND cell EEPROMs in order to achieve greater storage capacity. Miniaturization of memory cell transistors is pursued positively and continuously at the risk of reducing the operational reliability of NAND cell EEPROMs. The main cause for the shortcoming is undesirable entry of hot holes into the gate insulating film.
More specifically, as the integration density of memory cells becomes higher, the occupation area of each memory cell on the substrate is forced to decrease. Obviously, the gate insulation film lying between the substrate and the floating gate electrode is required to be thinner accordingly. The use of thin gate insulation film of the memory cell transistor will cause the generation of an abnormally high electric field near the drain in an erase operation. Hot holes are thus produced. If such hot holes enter the gate insulation film undesirably, the basic characteristics of the memory cell transistor change physically, causing the cell characteristic to be varied within the NAND cell unit. This causes the operational reliability of the EEPROM to decrease. In the worst case, the device life itself will be shortened seriously.